1. Field of the Invention The present invention relates to an apparatus for controlling group supervisory operation of elevators which is capable of centrally controlling a plurality of elevator cars in order to make them run efficiently and, in particular, to a highly reliable apparatus for controlling group supervisory operation of elevators which is capable of preventing a considerable decrease in group control functions when an elevator develops a fault.
2. Description of the Related Art
FIG. 4 is a block diagram showing the construction of a conventional apparatus for controlling group supervisory operation of elevators which is, for example, disclosed in Japanese Patent Laid-Open No. 59-124667. In FIG. 4, reference numeral 1 denotes a first computer which has a CPU 1a, a ROM 1b, and a RAM 1c. Likewise, reference numeral 2 denotes a second computer which has a CPU 2a, a ROM 2b, and a RAM 2c. Reference numeral 3 denotes a fault detection logic circuit, connected between these first and second computers 1 and 2, for monitoring the operating status thereof. Reference numerals 4a and 4b each denote a peripheral interface adapter (PIA) employed as a programmable general-purpose input/output interface element. These adapters 4a and 4b are respectively connected to the first computer 1 and the second computer 2 and controlled by the CPUs 1a and 2a, respectively. Reference numerals 5a, 5b. . . 5h each denote a car control apparatus for controlling the running status of each of a plurality of elevator cars (not shown). Reference numeral 6a denotes an input/output bus connected to a PIA 4a or 4b via a switch 7a and connected to a hall call registration button HB. Reference numeral 6b denotes an input/output bus connected to a PIA 4a or 4b via a switch 7b and connected to a hall call registration lamp HL. Reference numeral 6c denotes an input/output bus connected to a PIA 4a or 4b via a switch 7c and connected to each of the car control apparatus 5a, 5b. . . 5h. Reference numeral 6 d denotes an input/output bus connected to a PIA 4a or 4b via a switch 7d and connected to each of the car control apparatuses 5a, 5b. . . 5h. These input/output buses 6a to 6d are controlled by the PIAs 4a and 4b. Switches 7a to 7d form an input/output bus automatic switching apparatus 7 which operates in response to the detection output from the fault detection logic circuit 3.
The switches 7a to 7d are kept in a state shown in FIG. 4 when no fault of either the first computer 1 or the second computer 2 is detected by the fault detection logic circuit 3. That is, input/output buses 6a, 6b, and 6c are each connected to the PIA 4a and placed under the control of the first computer 1 and the input/output bus 6d is connected to the PIA 4b and placed under the control of the second computer 2. However, if the second computer 2 should develop a fault in a state in which the first computer 1 is operating normally, because the switch 7d is switched by the detection output from the fault detection logic circuit 3, the input/output bus 6d for communicating with car control apparatuses 5a, 5b. . . 5h is connected to the CPU 1a via the PIA 4a, placed under the control of the first computer 1, and disconnected from the faulty second computer 2. In contrast, if the first computer 1 should develop a fault in a state in which the second computer 2 is operating normally, because the switches 7a, 7b, and 7c are switched by the detection output from the fault detection logic circuit 3, the input/output buses 6a to 6d are connected to the second computer 2, placed under the control of the second computer 2 and disconnected from the faulty first computer 1.
In such a conventional apparatus for controlling group supervisory operation of elevators as described above, the construction of hardware for switching the input/output of the input/output buses is extremely complex, and the reliability of the input/output path through which signals are input and output decreases. Also, as the group control functions have improved in recent years, the amount of control information handled by the first and second computers 1 and 2 has increased and the amount of data transmitted between the two CPUs 1a and 2a has also increased. Therefore, such an arrangement of separate buses is problematical in that it is not possible to transmit a large amounts of data with high efficiency.